Fast SiC FETs just got faster

  • Oct 24, 2018
  • UnitedSiC

By Dr. Anup Bhalla, VP Engineering at UnitedSiC

You’re going to need a better oscilloscope…

The latest SiC switches are fast – not merely ‘faster’ but an order of magnitude better than silicon, for parts with similar headline ratings. This stems from a much smaller comparative die size for SiC, giving lower device capacitances while maintaining heat dissipation capability due to its 3X better thermal conductivity. The smaller chip sizes for SiC vertical devices compared to 650 V/1200 V Silicon devices, are a result of the 10X higher critical E-field at breakdown. UnitedSiC cascodes use SiC JFETs which are another 2X smaller than the best available SiC MOSFETs. In test circuits with rise and fall times measured in nanoseconds, you have to seriously think about the bandwidth of oscilloscopes to even see the real edge rates.

This is good news for efficiency in switched-mode power conversion. While voltages and currents transition between high and low levels, there is transient power dissipation, which can peak to kW but is averaged down inversely with switching frequency. As modern converters can now switch above 1 MHz though, that transient dissipation needs to be kept as low as possible with rapid switching.

Reality kicks in

Its common now to see edge rates for wide band-gap (WBG) device such as SiC FETs measured to be over 100 kV/µs and 3000 A/µs but is this useable?  Series stray inductance in a TO247 based half-bridge can easily be 50nH. High school math tells you that V = -Ldi/dt so that 50nH drops 150V with 3000 A/µs, appearing as drain voltage overshoot. Similarly, a stray drain capacitance of just 10 pF would cause 1 A current pulses from 100 kV/µs causing problems with ohmic losses in heat sinks! FET Source inductance also causes a transient voltage opposing gate drive with risk of spurious turn-on. A more insidious problem is internal to the FET where fast transitions can cause parametric oscillation and chaotic behaviour. For these reasons, SiC FETs often have internal gate resistance deliberately added to slow the edges with recommendation for even more external resistance to selectively slow on- and off-drive voltages.

Addressing the problem with SiC FETs cascodes

You can mitigate some of the problems by using SiC cascodes (as shown in Figure 1: co-packaged low-voltage MOSFETs with a SiC JFET), providing a fast, normally-OFF device with effectively zero gate-drain capacitance CGD.

Figure 1: SiC JFET cascode UF3C half-bridge with snubbers

External gate resistors R(ON) and R(OFF) allow edge rates to be controlled to reduce dV/dt and di/dt.  This is a very practical solution and can be used to upgrade existing systems using standard Si MOSFETs or even IGBTs for better efficiency while keeping the existing gate drive circuitry. Slowing edge rates with external gate resistors does have its problems though – they effectively introduce delays between control IC outputs and the switch gate, limiting minimum on-time and hence control range and operating frequency. Response time to shutdown commands on faults is also delayed. For new designs that need to operate at high frequency to get the full WBG benefits, this is a serious problem.

Make way for fast cascodes – UnitedSiC UF3C SiC FET series

Recent research at UnitedSiC has shown that ‘taking the brakes off’ a SiC JFET cascode with faster JFETs and low values of external gate resistors, used with simple RC snubbers, increases switching speeds and efficiency while adequately limiting voltage overshoots. You might think that this just transfers dissipation simply from the FET to the snubber but tests have shown that the snubbers can be quite small to achieve the voltage limiting effect. The JFET improvements lead to 50 percent lower reverse recovery charge, Qrr, which leads to lower turn-on losses relative to UJ3C general purpose devices.

These ‘FAST’ devices from UnitedSiC, making up part of the new UF3C series, can be used with snubber resistor values of typically five or ten ohms and capacitors down to 47pF. Actual values recommended vary with device type and the end application with hard switched active rectifiers, totem pole PFC and similar circuits seeing most benefit. A ‘rule of thumb’ is that the capacitor is set at about three times the device COSS. When upgrading existing designs, positions for snubbers will often already be present and the values using the UF3C parts will normally be much smaller physically and of course, lower cost.

Putting some figures on the performance, Figure 2 shows some comparative total switching losses for various devices in the 1200 V/ 35 mOhm class in TO-247 packages. The UF3C120040K3S device with 33 ohm gate resistor and a snubber of 330 pF and 5 ohms shows excellent results across the entire load range, and it is often possible to just use a single Rg and simpler driver.

Figure 2: EON+EOFF comparative values including snubber loss

Figure 3 shows the measured loss in the snubber resistor for the UF3C120040K3S. The losses represent a very small fraction of the total switching loss, since the required capacitances are quite small.

Figure 3: Snubber resistor loss as a fraction of EON+EOFF switching loss

Best of both worlds

You can have the efficiency benefits that high-speed switching offers without the risk of voltage stress from overshoots with small snubbers using the new UF3C series of SiC cascodes. The fact that the devices are compatible with a wide range of Si and SiC gate drive voltages and also have guaranteed avalanche ratings is a bonus.