Semiconductor lead forming is necessary in many designs. This blog talks about pitfalls to avoid and recommendations to follow for reliable results.
We’ve all done it in the lab – a through-hole power transistor needs its leads forming to fit a breadboard and we reach for the pliers. We remember just in time to reconnect the ESD wrist strap, eye up the jaw angles then bend away. The odd staggered pitch isn’t going to fit so we straighten the leads and try again, this time remembering to hold the leads with the pliers and bend against them with a ‘calibrated’ thumb. That looks better, but then a lead falls off – metal doesn’t like a zero-bend radius, especially the second time around. You wonder, do they still make round-nose pliers?
Old-timers learn how to get a workable result with their prototypes but in the production environment, lead forming needs to be better controlled. The consequences otherwise can be lead cracking, plating de-lamination or damage to the device molding, allowing moisture ingress and eventual failure in service.
But surely everything is surface-mount these days? Perhaps it would be good if it were, but the use of TO-style leaded packages isn’t going away anytime soon, especially in high power products. Anyway, engineers like the idea that expensive stressed parts can be changed out with a screwdriver, cutters and a 100W soldering iron. Why change them out? Because they fail – maybe because they are not formed correctly. The “chicken or egg” question starts to crop up at this point.
Some designers hedge their bets and use TO- packages with their leads formed into ‘gull-wing’ or C-shapes so they can get the best of both worlds: a screw-attached heatsink and a surface mount termination (Figure 1). They do risk tearing the traces off the board though with movement from differential material expansion with changing temperatures in normal operation.
Lead bends give strain relief but the idea of deliberately designing for a continuous flexing of a copper lead is not attractive and how much strain relief is enough? Even with JEDEC-compliant packages, thickness of the lead base material can vary +/-20% and the typically-tin plating could be from 300 to 1200 µin thickness, so stiffness is going to vary quite dramatically. Copper is a hard metal anyway, and when used for device leads, it has to be alloyed and tempered to a half-hard condition. I wonder what the tolerance is on ‘half’?
Then there is the problem of reflow temperatures and a lack of moisture sensitivity level (MSL) rating for a leaded device used as a surface-mount type. In practice, the leads may end up being manually soldered to get around these issues, which defeats the point a little.
There are some guidelines that at least explain how to lead-form without damage to the device itself. There are some no-no’s; leads should never be bent laterally (Figure 2) and should always be clamped so that a bend is not directly against the component body.
Clamps will be recommended that don’t touch the plastic material of the package and that avoid abrading the plating or exposing bare copper, although the bending tool face will inevitably at least ‘shine’ the plating surface. Distances of bends from the device body will be specified, taking into account any built-in standoffs along with a minimum bending radius, often quoted as a multiple of the width or thickness of the lead. The tooling and workplace will be required to be clean and suitably ESD protected.
UnitedSiC  markets wide band-gap semiconductor devices in various leaded formats: TO-220, TO-247 (three lead and four lead), TO-264 and more. They have a useful application note, AN0021: ‘Through-hole lead bending’  which gives a summary of the pitfalls and recommendations when bending their device leads, helping you to form corners reliably, not cut them.
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