By Mike Zhu, Application Engineer, UnitedSiC
The increase in demand for high efficiency, high power density and system simplicity makes silicon carbide (SiC) FETs an appealing choice for power engineers due to their fast switching speed, low RDS(on) and high voltage rating.
However, the fast switching speeds of SiC devices causes higher VDS spikes with longer ringing durations, which introduces more EMI at high current levels. For engineers working in high-power applications, such as EV and renewables, this is going to be a concern when trying to improve efficiency and unlock the full potential of this advanced technology without unnecessarily complicating designs.
What is VDS spike and ringing?
The root cause of VDS spike and ringing is the parasitic inductances. If we take a look at a typical turn-off waveform of a SiC MOSFET (figure 1), the gate-source voltage (VGS) is from 18V to 0V, the drain current (ID) is turned off at 50A, and the bus voltage (VDS) is 800V. Due to the faster switching speed of SiC MOSFETs, there will be a high VDS spike and a long ringing duration. The high VDS spike will reduce device margin to handle voltage distress from conditions such as lightning and sudden load changes. The long ringing duration will introduce more EMI. This phenomenon is more noticeable at high current levels.
A standard solution to suppress EMI is to reduce the current rate of change (dI/dt) by using a high gate resistance (RG). However, this method will force the trade-off between efficiency and EMI. In fact, using high RG dramatically increases switching loss.
Another solution is to reduce the power loop stray inductance. However, it requires the redesign of the PCB layout and use of smaller packages that are less inductive. Besides, there is a limit to how much we can minimize the power loop area on the PCB, and there are safety regulations that set the minimum spacing and clearance distances. Also, by using smaller packages, we sacrifice thermal performance.
We also have the filter design to help us meet the EMI requirement and ease the trade-offs in the system. Beyond that, we can use control methods to reduce EMI; the frequency dithering technique, for example, reduces EMI by spreading out the noise spectrum of the power supply.
A more effective and efficient approach is to employ a simple RC snubber, which relieves the design challenges and unleashes the full power of SiC devices. This simple solution can be shown to effectively controls VDS spike and ringing duration with higher efficiency across a wide load range and negligible turn-off delay.
Thanks to faster dv/dt and extra Cs, snubbers also have a higher displacement current, meaning less ID and VDS overlap at turn-off transition.
We can see evidence of this using a double pulse test (DPT) to study the effect of the snubber. It is a half-bridge configuration with an inductive load. Both high-side and low-side use the same device: VGS, VDS and ID are measured from the low-side device (figure 2).
The current transformer (CT) measures both device and snubber current. Therefore, the measured switching loss includes both device switching loss and snubber loss.
If a snubber is used, it is a 200pF capacitor connected in series with a 10Ω resistor across the SiC MOSFET’s drain and source.
First, let’s compare the turn-off (figure 3). For the same device in figure 1, the left waveform is using an RC snubber and low RG(off), and the right waveform uses high RG(off) but no snubber. Both methods limit the turn-off VDS peak spike voltage; however, the snubber uses 33ns to damp the ringing, while high RG(off) still has over 100ns ringing duration. Also, the snubber has less delay time than using high RG(off). Therefore, the snubber is more effective to control both VDS turn-off spike and ringing duration at the turn-off.
On the turn-on side (figure 4), if we compare between the waveform with an RC snubber and RG(on) of 5Ω and a one without a snubber, we can see that using snubbers slighting increases the peak reverse recovery current (Irr) from 94A to 97A. Other than that, it has a negligible effect on the turn-on waveforms.
This suggests that the snubber is more effective than high RG(off) in control of the VDS spike and ringing duration. But could the snubber be more efficient? (figure 5)
At 48A we find that the high RG(off) has more than twice the turn-off switching loss than using snubber with low RG(off). Therefore, the snubber is more efficient in turn-off because it allows faster switching while providing better control of VDS spike and ringing.
If we look at turn-on switching loss, the snubber slightly increases the Eon by 70µJ on average. Therefore, to give a full estimation of the overall efficiency, we need to add Eoff and Eon together and compare the Etotal (figure 6). When the device is switching at full speed, it is clear that above 18A the snubber is more efficient. For a 40mΩ device switching at 40A/40kHz, the difference in switching loss between using high RG(off) and low RG(off) with a snubber is 11W per device.
So we can conclude that the snubber is more effective and more efficient than using high RG(off).
As we enter the 4th generation of SiC devices, this simple design solution will continue to offer even lower total switching losses while optimizing system power efficiency.
You can find out more about how the simple snubber can unleash the optimal efficiency in UnitedSiC SiC devices in our recent webinar – Minimizing EMI and Switching Loss for Fast SIC FETs.
You can view the full webinar here: https://unitedsic.com/events/webinar-minimizing-emi-and-switching-loss-for-fast-sic-fets/
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