SiC – The Speed Challenge

  • Aug 04, 2022
  • UnitedSiC

Wide band-gap semiconductors of different technologies in power converters are often compared by which has the fastest switching speed or edge rates. This can enable higher operating frequency with lower losses and smaller power converter magnetics, which sounds like a good thing. In the real world though, faster dV/dt and di/dt can be a headache when you want to meet EMI specs – the smallest value of track or parasitic inductance along with circuit capacitances produces ringing, and WBG technology is less appealing if you must add multiple large, expensive filters to pass emissions limits. The ringing also produces voltage overshoot which can be damaging, or at least reduce voltage safety margins, forcing the use of higher-rated and more expensive devices, usually with higher conduction loss.

Slowing edges increases dissipation

In practice, edge rates must be controlled to avoid overshoot stress and a common solution is to add gate resistance, often different values for on- and off-transitions using diode gating. This certainly reduces voltage and current edge rates and the initial voltage overshoot, but increases voltage/current overlap on turn-off with consequent increase in power dissipated and it does nothing for the ring duration, which happens after the turn-off transition and the gate drive has settled. Attempts to reduce inductance to minimize ringing can also be thwarted by practical layouts required to achieve safety separations and device package types chosen.

Snubbers are the front-runner

A better solution with SiC FETs is to use a small RC snubber across the device for hard-switching applications, and for soft switching, just a capacitor at the switch along with a RC snubber across the DC-link rail. Even with small snubber RC values, ringing can be effectively damped while limiting overshoot and keeping losses low. Figure 1 shows a snubber controlling overshoot in a hard-switching circuit to the same value as a 5-ohm gate resistor, but with much better damping. Turn-off energy Eoff is halved compared with just a gate resistor, but turn-on energy Eon does increase by about 10%, so for a fair comparison, we look at Etotal showing that overall, the snubber approach is more efficient while giving the damping we need. In a practical circuit, if ID were 40A at a switching frequency of 100kHz, a 40-milliohm SiC FET using a snubber and no Rgoff would dissipate 10.9W less than with just 5-ohms Rgoff. In both cases Rgon is set at 5-ohms. For soft-switching applications, losses with a simple capacitor snubber are even lower.

Figure 1. Snubber controlling overshoot in a hard-switching circuit

You can see from the waveforms that the gate resistor solution also produces an increased delay from gate drive to drain voltage rise, about 104ns compared with 33ns, which would limit minimum duty cycle achievable and the operating range of high-frequency converter circuits.

SiC FETs user guide speeds snubber value selection

The snubber value is easily calculated from observation of the ringing waveform – just add a small known snubber capacitor C1 of around 3x the SiC FET data-sheet output capacitance Coss and see the frequency change and then deduce parasitic capacitance C0, which includes Coss, strays and any heatsinking contribution. Parasitic inductance L can now be found from the L-C resonance equation. Possible snubber starting values are C1= 2 x C0 and R=√(L/(C0+C1)). Recommended values can also be found on the UnitedSiC website here: SiC FET User Guide. Values are given for different products for a range of frequencies in hard- and soft-switched LLC and PSFB applications, and can be tuned for an acceptable combination of efficiency, voltage stress and EMI.

So, you can strap-in and let your power converter circuit speed up to high frequencies and get the size, weight and cost benefits of smaller filtering and power stage magnetics. All this using the optimum SIC FET voltage rating for the task and with EMI contained to manageable levels.