By Anup Bhalla, VP Engineering at UnitedSiC

The cascode has proved to be a very useful structure since it was conceived way back in the vacuum-tube age to overcome the Miller effect, which causes a signal source to see an input capacitance much greater than the parasitic capacitances present in the device. Of course, the Miller effect – discovered in 1920 by John Milton Miller[1] – did not go away with vacuum tubes. It has persisted to this day as a consequence of the parasitic capacitances intrinsic to all transistors. By limiting high-frequency performance, it restricts the switching speed of today’s power-conversion circuits.

As designers seek to leverage the enhanced energy efficiency, thermal performance and ruggedness of silicon carbide (SiC) technology for switching power supplies, converters and inverters in all kinds of equipment, the cascode has again proved extremely valuable. A cascode combination of a low-voltage silicon MOSFET and high-voltage SiC JFET in the same package can be controlled using ordinary MOSFET gate-drive signals generated by an ordinary MOSFET gate driver. Moreover, the cascode is normally off, and hence well-suited to use in power circuits, although the JFET is naturally a normally-on device. This enables designers to take advantage of the SiC Cascode’s superior body diode performance, compared to a conventional SiC MOSFET.

However, although the cascode effectively circumvents the Miller effect, it does so by stabilizing the drain voltage of the input transistor, and not by eliminating the parasitic effects intrinsic to the transistors themselves: those capacitances are still there, as shown in figure 1.

As a low-voltage device, the silicon MOSFET has low RDS(ON) that minimizes its impact on energy loss: the high switching performance and favorable RDS(ON) of the SiC JFET, in relation to its voltage and current ratings, still dominate. On the other hand, there can be a significant difference between the MOSFET capacitance (C_DS Si) and that of the JFET (C_DS SiC). This can cause some problems if using cascodes in very high-voltage switching circuits.

If C_DS SiC is significant relative to C_DS Si, a high voltage can develop at the Si MOSFET drain when both devices are off, which can exceed the MOSFET breakdown voltage, leading to failure of the device. In addition, if C_DS SiC has a finite value, it can allow pulses of current to pass that may cause spurious turn-on of the JFET, and so prevent Zero Voltage Switching (ZVS) in soft-switching topologies. It is also possible for ‘divergent oscillations’ to occur at high-current turn-off, which can destroy the JFET.

There are basically two ways to address an imbalance: increase one, or reduce the other. Huang et al.[2] proposed adding capacitance, and demonstrated improvement in high-current turn-off behavior. The position and value of this added capacitance are critical.

At UnitedSiC, we are addressing the challenge through one of the most promising techniques for reducing the capacitance of SiC JFETs. Our vertical channel construction, shown in figure 2, allows C_DS SiC to become effectively negligible. Leveraging this technology, the SiC cascode can approach the performance of an ideal switch even more closely.

We can improve the performance of SiC cascodes even further, through innovations such as stacking the MOSFET and JFET dies. SiC JFET fabrication achieves high yield per wafer, allowing cascodes to be built cost-effectively despite containing two co-packaged devices. Stacking can unleash extra cost savings, while at the same time further reducing internal package inductances to allow even greater speed and efficiency.

The SiC cascode has already taken a leading role in realizing the advantages of silicon carbide in important power-conversion applications, including renewable energy generation, transportation, consumer tech and smart industry. Nearly 100 years after its inception, the cascode continues to help overcome engineering challenges, and there is still scope to advance and improve these important devices.

[1] http://www.mit.edu/~klund/papers/jmiller.pdf

[2] 1. X. Huang, W. Du, F.C. Lee, Q. Li and Z. Liu, “Avoiding Divergent Oscillation of a Cascode GaN Device Under High-Current Turn-Off Condition”, IEEE Trans. Power Electron., 2017.