This application note explains how the breakthrough performance of UnitedSiC 750V Gen 4 SiC FETs enables a simple design of highly efficient Totem-pole PFC. Efficiency measurements on the developed unit will demonstrate a 99.3% efficiency rating. Insight into the losses is provided by the new UnitedSiC FET-Jet Calculator on-line tool, which are shown to match the actual measurements quite well. Finally, we discuss how the high efficiency of SiC FETs allows further BOM cost reduction for Totem-pole PFC.
Pick-and-place machines place surface mount technology (SMT) devices on a circuit board very quickly and with excellent precision. This combined with a highly repeatable solder process in a reflow oven results in low assembly cost with superior mechanical reliability. These benefits are further combined with reduced stray inductance and package resistance (better electrical and EMI performance) in SMT power devices. The use of SMT power devices is enabled in part by the low power loss of SiC devices. This application note addresses the construction, land patterns, moisture sensitivity level, and reflow solder profile for UnitedSiC SMT devices.
This Application Note discusses the ESD capabilities of UnitedSiC’s transistor offerings.
This Technical Product Overview presents the new Gen 4 SiC FET attributes, i.e., new 750V VDS option and important performance “Figures of Merit” that deliver an overall superior performing SiC FET product that power designers can now benefit from in their next-generation system designs.
This SiC FET user guide presents practical solutions and guidelines for using RC snubbers with fast switching SiC devices. The solution is verified by experimental double pulse tests (DPT) results. The snubber loss is precisely measured to assist users in computing the power rating of the snubber resistor. The beneficial impact of the snubber is analyzed for both hard switching and soft switching applications.
For certain applications, such as motor control, it is important to slow dV/dt down during switching. Too fast and it would cause a high voltage spike on the motor, which could damage the winding insulation and so, reduce motor life. In this app note, Zhongda Li from UnitedSiC, compares three different dV/dt control methods.
Three-level diode neutral point clamped (3L-NPC) and active neutral point clamped (3L-ANPC) inverters share fundamental features, including an operating voltage limit that is higher than the individual power semiconductor ratings, reduced switching loss, and three-level output voltages. Neutral point voltage balancing algorithms remain unchanged. In the 3L-ANPC, two FETs replace two diodes in each leg, and therefore 3L-ANPC is higher cost. Depending on modulation, the additional 3L-ANPC switch states can be used to reduce power loss, double the output frequency, and/or affect switch utilization.
One unique characteristic of UnitedSiC Gen 3 SiC FETs is that its switching losses and Qrr decrease at elevated temperature, making the device more efficient once it heats up. This paper explains in detail the reason behind this characteristic.
It is often necessary for board assemblers to bend the leads of a through-hole technology (THT) device when constrained by heat sink orientation, board and system space, etc. While the package may be formed into different configurations for board mounting, care must be taken in order avoid damage such as plating strip-off, cracked package, or delamination. This application note contains options and guidelines for reliable lead bending.
There are multiple variants of three-level neutral point clamped inverters. Most are derivatives of two circuit topologies: one with four series-connected FETs and two clamp diodes, the other with two series-connected FETs and two clamp FETs. The first one is diode neutral point clamped but simply called neutral point clamped (NPC). The second one is transistor neutral point clamped (TNPC), and the phase leg schematic resembles a sideways letter T. There are different tradeoffs between these two topologies, but in the end the gate drive requirements and implementation are very similar.
The emergence of fast switching WBG devices has dramatically enhanced power density in a range of power conversion circuits such as active rectifiers, LLC bridges, Phase shifted full bridges, Dual active bridges to name a few. These circuits form the backbone of efficient AC-DC and DC-DC stages in battery chargers for EVs, forklifts, solar inverters and power supplies, especially where
power density is key.
Control theory is one of the many aspects of electronic theory required for power electronic design. With the ever increasing popularity of digital control, it is important to have a good understanding of the basics of digital control. Many textbooks have been written about system modeling and control theory, but what can be difficult to find is a clear explanation of how to take an existing continuous-time model and convert it to something that can actually be programmed
into a microcontroller.
The 80 Plus certification program is used to classify power supplies in terms of efficiency and power factor. Supplies with the highest overall efficiency and power factor can be certified to the 80 Plus Titanium level. Titanium power supplies have the lowest energy cost, and are one of the pieces in improving operational computer efficiency.
The design of a renewable energy inverter involves many tradeoffs, including cost, electrical specifications, efficiency, features, reliability, installation cost, etc. Adding to these assorted considerations is the radically improved performance of SiC versus silicon-based semiconductors and their cost differences, which makes evaluating various topology options like comparing apples to oranges and pears.
Power MOS devices, which include power MOSFETs of various construction materials and gate structures, as well as JFETs and IGBTs are three-terminal devices with current flow controlled by the gate. In most power electronic applications, the gate is driven to either block current flow with the device fully off; or fully on with minimal conduction loss.
This document provides recommendations for soldering and rework of UnitedSiC through-hold technology (THT) devices, including (but not limited to) TO-247 with three or four leads, and TO-220. Included are recommendations for production assembly soldering as well as rework.
Bridgeless totem-pole PFC can be used to improve efficiency over conventional boost PFC by reducing the number of semiconductor devices in the conduction path from three to two. Silicon based totem-pole PFC have been limited to critical conduction mode (CrM) due to the high Qrr of silicon switches.
The unique combination of features of the silicon carbide (SiC) cascode opens possibilities for new circuits, or for expanding the operating boundaries of existing circuits. The phase shift full bridge (PSFB) is a perfect example, now capable of operating efficiently and economically with 800 V input.
Systems that incorporate High Voltage Rails (~ 800 V) are typically controlled by circuitry that utilizes much lower voltages. Microprocessors, communication protocols, and sensors require a variety of voltages. A common approach to generate these voltages is with the flyback topology. In this design, a 1.7kV JFET in the cascode configuration is used as the main power switch in a flyback utility power supply.
SiC junction barrier schottky (JBS) diodes, as majority carrier devices, have very different turn-off characteristics from conventional Si PiN diodes. The specification data presented in the datasheets are not enough to fully cover the turn-off characteristics of SiC JBS diodes. This application note presents comprehensive experimental results to reveal the turn-off behavior of SiC JBS diodes and serves as a supplement to the datasheets.
United Silicon Carbide provides standard text based SPICE models to all their commercially released products. To fully utilize these models they need to be imported into a circuit simulator. This application note details the process to add UnitedSiC models to LTSPICE, and apply them to a simple example.
The performance improvements of Silicon Carbide switching devices compared against standard Silicon devices are well documented. What can be confusing are the drive requirements for the various SiC devices and the variation between suppliers. This document is designed to be used in conjunction with the data sheet to enable designers to confidently design with United Silicon Carbide (UnitedSiC) normally on xJ Series 1.2kV JFETs.
The high switching speeds and low RDS(ON) of high-voltage SiC JFETs can significantly improve the efficiency and power density of many power conversion applications. However, the conventional view of these devices is that, despite the parametric advantages, JFETs are difficult to implement due to non-standard drive voltages and a lack of an intrinsic diode when switching inductive loads.
With the introduction of wide bandgap switching devices, good efficiencies at higher switching frequencies become attainable, while producing more cost effective solutions by lowering the required inductance. This article will explore the design tradeoffs for efficiency and power factor in implementing designs at higher frequencies (>75kHz).
In an attempt to improve the efficiency and power factor of computing power supplies, the computer industry has created a voluntary certification program called “80 Plus”. In this application note, a silicon carbide cascode switch and boost diode will be evaluated in a 1 kW hard switch Power Factor Correction (PFC) board with respect to its suitability in 80 Plus applications.
Offline converters present a challenge in starting up, due to the mismatch between the high voltage input, and the low voltage power supply requirements of the controller IC. A typical application uses a string of resistors, Zener diodes and a high voltage BJT combination to generate ~ 12 V to power the controller until the feedback winding can generate enough energy to power the IC at an operational voltage. This application note will describe a self-generated startup voltage that can be used by taking advantage of a cascode configuration.
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