The internet doesn’t know who first coined the term ‘bridgeless totem-pole power factor correction stage’ but it must have been invented and named in a moment of whimsy and inspiration – in an AC/DC power supply, the circuit can implement power factor correction and effectively boost efficiency by as much as 2% at low line, by removing the need for a line AC bridge rectifier. Let’s investigate it further and call it ‘TPPFC’ to keep the character count within bounds.
Ideal switches are needed
The TPPFC architecture was first demonstrated around 2011 and with ideal switches and low loss magnetics, the circuit can theoretically approach 100% efficiency. It was an idea before its time though, as semiconductors for the high-frequency boost switches have not been ‘ideal enough’, at least until recently. The problem is the trade-off between conduction and switching losses – for lower on-resistance and less conduction loss, a larger effective die area is needed, but this leads to higher device capacitances and higher dynamic losses. There is also the problem that the TPPFC must operate in a ‘hard-switched’ continuous conduction mode at medium power levels upwards to keep peak currents manageable and this requires recovery of stored charge in the body diode of switches. When silicon MOSFETs are used, the charge is significant and the resulting dissipation is high enough to make the circuit not worth any small net gain, especially when the cost and complexity of switch drive and control are factored in.
We’re getting there with wide band-gap semiconductors
That 2% theoretical efficiency gain is attractive though – server efficiency standards such as ‘80+ Titanium’ mandate a total of just 4% losses end-to-end in an AC/DC power supply at 230VAC and 50% load. With typically 2% allocated to the AC front end, the TPPFC had to be revisited with new technology to push its performance and with wide band-gap switches, the picture changes. Silicon carbide and gallium nitride are the candidates and while a SiC MOSFET has an 80% reduction in reverse recovery compared with silicon, GaN has effectively none. Output capacitances are also lower than a silicon MOSFET because the WBG die are generally smaller than silicon for the same voltage class. This is a direct result of the higher critical Electric Field of WBG materials which handle the same peak voltage with much thinner, more heavily doped voltage supporting regions, with a resulting lower on-resistance. The low-loss advantages of SiC and GaN can be summarised by the figures of merit RDS(on) x A and RDS(on) x EOSS, the first indicating the trade-off between on-resistance and die area and the second between on-resistance and energy lost on switching due to output capacitance.
WBG devices have made the TPPFC stage viable and the circuit is now common, but all is not rosy in the garden yet, as those headline advantages of SiC and GaN hide some practical implementation difficulties. SiC MOSFETs have a low recovery charge sure, but the body diode has a very high forward voltage drop, adding some losses back in. Gate drive is also sensitive with threshold hysteresis and variability and the recommended high voltage for full enhancement is perilously close to the absolute maximum. GaN devices conversely have a low gate threshold voltage risking spurious and catastrophic turn-on with switching transients. This can be alleviated by a negative off-drive voltage but this causes an excessive voltage drop when the device conducts in reverse before the channel is enhanced, adding to losses. GaN is also still relatively expensive.
SiC FETs – as good as it gets
There is another option though, semiconductor manufacturers have known for decades about the ‘cascode’ technique of combining a high voltage switch with a low voltage type to get an edge in both conduction and switching losses. In its wide band-gap incarnation, a normally-on SiC JFET is paired with a low voltage silicon MOSFET to produce a device which is normally-off, with a non-critical gate drive, a low-loss body diode and all the benefits of a WBG device. It is available from UnitedSiC as a ‘SiC FET’ and can switch blisteringly fast with a very small die size for low capacitances and low dynamic loss. The JFET effectively sets the conduction loss and its simple vertical construction enables low on-resistance, even with the small die size. The proof of the benefits is in those figures of merit. Figure 1 shows how the 750V SiC FET stands up against 650V SiC MOSFETs.
SiC FETs in the totem-pole PFC circuit not only yield the promised gains in efficiency but also are easy to implement. You could say that the combination of topology and SiC FET switch is ‘totemic’ – symbolic of the best achievable.
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