UnitedSiC has focused on SiC JFET based cascodes due to the excellent properties of the cascode device from ease of gate drive, good body diode behavior to good short circuit handling. The key to the cost-performance benefit comes from the low RdsA of SiC vertical JFET compared to SiC Planar and Trench MOSFETs. We see that this difference will remain as both JFET and MOSFET technologies advance, both at 1200V and even more so at 650V. This is because the channel region becomes a greater contributor to device RdsA. With the release of Stack cascode chips in 2019, the assembly of UnitedSiC cascodes becomes equivalent to SiC MOSFETs in complexity. With these improvements, we see Cascodes as a long term solution for power electronics needing the benefits of wide band gap (WBG) switches.
The UnitedSiC FET uses a vertical SiC JFET with much lower RdsA than lateral GaN FETs, even at 650V. It can also be extended to much higher voltage ratings. The cascode device also uses a specialized custom LV MOSFET to simplify FET operation and offer gate drive compatability with all existing SiC MOS and Si IGBT/MOS switches. The main structural reason that UnitedSiC FETs are superior stems from the JFET structure with Cds=0, which eliminates the voltage divider problem during fast switching that affects the GaN cascode, and previous SiC cascode attempts.
The SiC MOSFET structure is quite familiar to most power supply and inverter designers, as well as device manufacturers. The SiC JFET is quite different to process, and creation of cascode products require more engineering effort, including special LV Si MOSFETs and advanced packaging. UnitedSiC is among the few manufacturers with all the required packaging, Si and SiC expertise in one team to accomplish this. Finally, SiC MOSFETs are easier to control with gate resistors, while SiC cascodes have a limited control range, requiring the UnitedSiC approach of application tailored devices. These devices then offer best-in-class performance.
UnitedSiC is studying whether this package or a surface mount gull-wing-lead top-exposed package is the right option to provide a low inductance, surface mount, peak thermal performance option. UnitedSiC devices are much smaller and lower loss than Superjunction MOSFETs and may benefit from smaller packages. These options will be added to our packaging line-up of D2PAK-3L, D2PAK-7L and DFN8x8.
UnitedSiC Cascode/FETs are commonly used in parallel to increase power output. The performance of the FET is dominated by the SiC JFET, that controls the switching speed and provides a device where Vth does not decrease with temperature and has a strong positive temperature coefficient of Rdson. These characteristics allow the device to paralleled very effectively, and de-sensitize it to variations in the low voltage MOSFET Vth etc.
The key to avoiding voltage over-stress in the LVMOS is to use a JFET device structure with Cds=0, to avoid any capacitive voltage divider behavior. Furthermore, the LVMOS is designed with a built-in clamp PN junction diode in each cell of the trench MOSFET which allows the device to tolerate large repeated avalanche events indefinitely. This is proven both by avalanche mode burn-in, as well as exposure to 1M cycle avalanche events with no parametric shifts.
For the SIC Cascode FET, turn-on speed can be increased by using higher Vgs(on), or lower Rgon. The device turn-on can be slowed with higher Rgon, lower Vgs(on). The turn-off is harder to adjust with Rgoff, although higher Rgoff will in fact slow down the device. It is better to use a small RC snubber, either on the DC bus, or across the device, to minimize overshoots and ringing with much lower degradation in switching loss.
The Eas capability of a SiC device will indeed depend on die size. However, in practical applications, what is more important is the ability of the device to handle high peak currents of low energy avalanche, which can occur during lighting strikes and other overstress events on the AC line. In this area, the SiC Cascode FET from UnitedSiC is excellent, because of the mechanism by which the JFET handles the avalanche but going into the active mode. Very high avalanche current density can be handled safely in repetitive mode, without any shift in device parameters and capacitances, much better than with traditional SiC MOSFETs where the gate oxide can be impacted.
We can expect AEC-Q101 products to be available for a 5-10-year period. It is always good practice to contact your local UnitedSiC sales office and plan your long-term needs for all products.
PCB layout guidelines are available from UnitedSiC applications engineering support. Some examples can be found in the design resources section and can also be obtained by purchasing the double pulse demo board. Generally, the layouts used for fast Si MOSFETs, SiC MOSFETs and UnitedSiC FETs are similar. If application requirements require layouts with higher loop inductance and long gate drive loops, we recommend snubber options that ease the path to using paralleled products with minimal issues.
Maximum operating frequency depends on the type of hard or soft switching being used. Due to high Eon losses in all switch devices, hard switching frequencies are kept below 100-200kHz. For soft switched circuits, 650V SiC Cascode FETs are in use at 500kHz. 1200V FETs can also be used at 200-500kHz, although most high efficiency circuits use lower frequencies.
The SiC MOSFET channel mobility is quite low, and its temperature dependence results in a decrease of channel resistance with temperature between 27 deg C and 125 deg C. This compensates the increase in drift layers resistance with temperature as is common for all ideal bulk conduction. The SiC JFET structure has a bulk channel with 10-20X higher mobility, and which leads to the lower RdsA. This mobility increases with temperature more in line with ideal bulk mobility. This makes the overall increase of Rds with temperature greater for SiC Cascode FETs. This makes the devices easier to parallel, and make it easier to realize robust short circuit handling capability.
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This is because for UnitedSiC SiC FET, most of the Qrr comes from the capacitive charge SiC JFET Coss. Since it is a capacitive charge, it does not increase with temperature. A very small portion of the Qrr comes from the LV Si MOSFET body diode, which does increase with temperature. So the overall effect was only 10% increase, very small.
This is because the UnitedSiC SiC FET has very small Cgd, so it tends to turn off very fast, which also gives you very low turn-off loss. So we found using around 20 ohm Rg,off, you can slow down the turn-off dv/dt to about 80V/ns, which is still quite fast, and gives you very low turn-off loss. So basically you can achieve the same or better turn-off loss as the conventional SiC MOSFETs, using a 20 ohm Rg,off.
All are pure tin plated.
The UnitedSiC Fast SiC FET series, UF3C/UF3SC, often need at least a bus snubber, and in cases of poor layout or when using 3L packages, they may require an RC snubber across the device. This user guide shows the appropriate gate resistors and snubbers we recommend. https://unitedsic.com/guides/UnitedSiC%20SiC%20FET%20User%20Guide.pdf
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